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Altera_Forum
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11 years ago

signal as loop termination condition

Hi all ; I am writing vhdl at quartus ii 32 bit v. 13.1.0 web edition for terasic d0 board. I am trying to write a time delay procedure but getting "VHDL Loop Statement error at <location>: ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Yes, this will never work. Loops unroll into hardware.

You need to think about the hardware you're trying to create, not the software style code. (Im guessing you're a programmer)

You need a counter in a synchronous process, and then finish when the counter reaches a certain value.

Another issue you have is that your design has no outputs. Then it actually does nothing on real hardware, and will synthesise to nothing (when you can get it to compile).