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Altera_Forum's avatar
Altera_Forum
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18 years ago

Setting the I/O bank voltage

I'm hoping some kind soul can help me out here.

I'm trying to build the reference design (originally built with Q-II 7.1) that came with my LPRP board. One of the problems is that Quartus II 7.2 complains

Error: Pin CLK_48_MHZ is incompatible with I/O bank 6. Pin uses I/O standard 1.8 V, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins....

The only way I've found to assign the VCCIO on the bank is inside the pin assignment editor, but even when I explicitly set the bank to 1.8 V it still complains the same. Note, there are no other pins in the bank and the bank assignment does show up in the .qsf file.

Now the currious thing is that setting the _default_ IO voltage (in device assignment) to 1.8 V and setting the other banks to 2.5 V works as expected.

Is the issue that this is a global clock and it's IO standard has to be compatible with the default?

At a loss here. The Quartus help is useless.

Thanks

Tommy

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Hi Tommy:

    My guess is you have one pin in that bank not assigned with an IO standard at all, and it's defaulting to 3.3V or 2.5V (depending on the device).

    Make sure all the pins assigned in bank 6 have 1.8V IO set. If you are missing just one, it will flag the bank in error, and depending on the sequence it reads in the pins, may be just flagging this clock pin as the error.

    I know I have a design compiled under QII 7.2 that has a clock on a 1.8 IO bank, and it seems to be ok. (Cyclone II/Cyclone III design)

    But if you miss one pin, it defaults to either 3.3V or 2.5V.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    @anakha: Thanks that could seem like a plausible, albeit odd, theory. To test it I painstakenly assigned all pins in the bank and gave then a 1.8 V I/O standard. Nope, it didn't work. Instead Quartus now complains about all of them.

    FYI, the LPRP has an DP3C25F324C8 and the bank in question is bank 6.

    I wonder if it could be related to the fact that there are dedicated programming pins in that bank. Still, it doesn't make sense to me.
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    I have listed the steps below to resolve this issue.

    The problem occurred because the external configuration device connected on those banks was defaulting to a 2.5V I/O standard in Quartus II. Quartus II 7.2 now has an option to define the Configuration bank pins I/O voltage specifically.

    The Steps are

    1. Open the project in Quartus II 7.2

    2. Select Assignments ---> Device "pull down menu"

    3. Press the Device & Pin Options "Button"

    4. Select the Configuration "tab"

    5. Select 1.8V in the Configuration device I/O voltage "pull down window"

    6. Select OK in both windows to exit

    7. Recompile the design
  • Altera_Forum's avatar
    Altera_Forum
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    18 years ago

    Blimey that was it! I dare say, Quartus' could have been more helpful here.

    Thanks Skravats
  • rjadh1's avatar
    rjadh1
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    7 years ago

    The issue happened on the grounds that the outside arrangement gadget associated on those banks was defaulting to a 2.5V I/O standard in Quarts II. Quarts II 7.2 currently has a choice to characterise the Arrangement bank pins I/O voltage explicitly.

    The Means are

    1. Open the venture in Quartus II 7.2

    2. Select Assignments - > Gadget "pull down menu"

    3. Press the Gadget and Stick Choices "Catch"

    4. Select the Setup "tab"

    5. Select 1.8V in the Setup gadget I/O voltage "pull down window"

    6. Select alright in the two windows to exit

    7. Recompile the structure.

    Electrical Engineer