RTL Viewer

If your code produces different results on every compile, then I suggest there is a problem with your code and practices. I never get "a lot of muxes" - I get exactly the hardware I expect.

You can only implement 1 architecture because it has to go into an FPGA. an output can only connect to one set of logic. You need extra logic to connect multiple architectures to an output, which would need to be defined in the VHDL, so you need somewhere that specifically selects the individual architectures.

The VHDL has to map to the hardware available. Not all VHDL is going to map to the hardware. No ammount of tickets is going to make that happen.

So far, I fell like you're trying to write software rather than hardware.

by the way, RTLView helps to find mistakes in code and provides some information about which path for data could be time-critical.

so you can change design before you will begin fitting.

@Tricky, I try to stay at top-level of abstraction. if I have trouble on the very first stage , why proceed to the second? I want the first stage will be comfortable.

When you end up debugging your code and quality of syhthesis is quite good for you then you have only 1 architecture which will be programmed in FPGA.

but how you will select the one architecture and say "it is good". do you know about it from the very start of project? if so you have experience (green, yellow, red marks under your name at forum ;) )

It's quite easy to work out the timing critical paths from the code. The largest amount of logic between registers will be the culprit.

I hardly ever use the rtl view unless I think there is some synthesis bug.

okay. the usage depends on background knowledge. You certain about your code - you don't use tool, but not me.

What i want i've already said (maybe sad ;) ). Tool usage depends on one's own.

the question still exist: if quartus compile as expected as many architecture as written why it can not open choosen one until you choose it explicit?

P.S. : I couldn't change my knowledge at speed of modern FPGA.

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@Tricky, do you know about it from the very start of project? if so you have experience (green, yellow, red marks under your name at forum ;) )

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You haven't seen FvM's rank, he is the highest decorated Altera lieutenant.

I think the best tool is you and that requires familiarity with tool and concepts. I wouldn't go your way to know ahead of fitter. I will design with minimum logic in between registers and pray. One design with its files and dependencies is far too much. If you are dealing with large projects contaings 100s of design module I wonder how can you design several versions just for testing. Where is Practicality, time factor, manager's mode???

@kaz, @tricky

we can end up with "why such tool exist?" and "why vhdl allow multiple architectures?"))

multiple architectures exist but it seems noone want to deal with it. it is subject to thread in VHDL section/not here.

When you have time to research or ,for example, you have good partner. why not? Even in "advanced synthesis book" there are several approach to adders/compressors, you choose only one for one entity or choose as many as you want, then make a final decision. Will you put in one file or among many files? will it be library at all?

i got answer how i can manage with my question in current environment. it is good enough.

and it seems that thread for now is mixed up with "usage rtlviewer tool" and "using vhdl architecture concept". Due to the very first question.

I appologize that you can not over-persuade me to take your position at 100%, but 70% :)

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@kaz, @tricky

we can end up with "why such tool exist?" and "why vhdl allow multiple architectures?"))

multiple architectures exist but it seems noone want to deal with it. it is subject to thread in VHDL section/not here.

When you have time to research or ,for example, you have good partner. why not? Even in "advanced synthesis book" there are several approach to adders/compressors, you choose only one for one entity or choose as many as you want, then make a final decision. Will you put in one file or among many files? will it be library at all?

i got answer how i can manage with my question in current environment. it is good enough.

and it seems that thread for now is mixed up with "usage rtlviewer tool" and "using vhdl architecture concept". Due to the very first question.

I appologize that you can not over-persuade me to take your position at 100%, but 70% :)

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Well I came to the conclusion that yes learners need different version of tools in order to learn best way. So yes I agree that having support for multiple architectures in one compilation will help. Altera wants profit and is not a charity. Universities need to raise issues like that and other issues like many beginners use buffer type io or bit type instead of std_logic. May be just the old things went through University programs, each professor copying his colleagues's previous slides. I am persuaded 100%

The statement of "multiple architectures exist but it seems noone want to deal with it" is incorrect, in fact configurations are covered in the first section of the LRM!

Similarly if you have create multiple architectures and they are always all compiled will mean that every architecture must be syntactically correct or the compilation will fail. I think this would cause more (justifiable) criticism than the way it currently works.

At the end of the day the vendors tools are limited by the LRM and the functionality of their competitors' tools, irrespective of who they are.