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Altera_Forum's avatar
Altera_Forum
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11 years ago

RTL Viewer

Hi. If I have one file written in VHDL with two different architectures could I see in RTL Viewer structure for each architecture? or the architecture shown in rtlviewer wil be randomly selected b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

@Tricky, I try to stay at top-level of abstraction. if I have trouble on the very first stage , why proceed to the second? I want the first stage will be comfortable.

When you end up debugging your code and quality of syhthesis is quite good for you then you have only 1 architecture which will be programmed in FPGA.

but how you will select the one architecture and say "it is good". do you know about it from the very start of project? if so you have experience (green, yellow, red marks under your name at forum ;) )