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Altera_Forum's avatar
Altera_Forum
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11 years ago

RTL Viewer

Hi. If I have one file written in VHDL with two different architectures could I see in RTL Viewer structure for each architecture? or the architecture shown in rtlviewer wil be randomly selected b...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

It's quite easy to work out the timing critical paths from the code. The largest amount of logic between registers will be the culprit.

I hardly ever use the rtl view unless I think there is some synthesis bug.