RTL Viewer

If your code produces different results on every compile, then I suggest there is a problem with your code and practices. I never get "a lot of muxes" - I get exactly the hardware I expect.

You can only implement 1 architecture because it has to go into an FPGA. an output can only connect to one set of logic. You need extra logic to connect multiple architectures to an output, which would need to be defined in the VHDL, so you need somewhere that specifically selects the individual architectures.

The VHDL has to map to the hardware available. Not all VHDL is going to map to the hardware. No ammount of tickets is going to make that happen.

So far, I fell like you're trying to write software rather than hardware.