Honored ContributorHi all.
Im new to FPGAs. I have built some circuit with ROM memory (added with MegaWizard). The problem is memory output port is in the High-Z state all the time. I have connected clock to 50M clock, and address bus to 10-bit binary counter. I have "uploaded" ROM init state file also. Can you help me?
Honored ContributorDo you have warnings in Modelsim related to unspecified ROM initialization file?
Honored ContributorI can't see nothing like that. But I attach all messages for query "ROM"
Honored ContributorPlease help me, I will go crazy :| Timings are OK. Whats wrong with configuration?
Honored ContributorHonored ContributorMemory list is empty. How I can load something?
Also I noticed that warning: "Warning (113007): Byte addressed memory initialization file "127.hex" was read in the word-addressed format"
