Altera_ForumHonored Contributor12 years agoROM at ModelSim - data port is in High-Z State Hi all. Im new to FPGAs. I have built some circuit with ROM memory (added with MegaWizard). The problem is memory output port is in the High-Z state all the time. I have connected clock to 50...Show Moremultiple-attachments.zip102 KB
Altera_ForumHonored Contributor12 years agoPlease help me, I will go crazy :| Timings are OK. Whats wrong with configuration?
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