Altera_ForumHonored Contributor13 years agoROM at ModelSim - data port is in High-Z State Hi all. Im new to FPGAs. I have built some circuit with ROM memory (added with MegaWizard). The problem is memory output port is in the High-Z state all the time. I have connected clock to 50...Show Moremultiple-attachments.zip102 KB
Altera_ForumHonored Contributor13 years agoDo you have warnings in Modelsim related to unspecified ROM initialization file?
Recent DiscussionsConnection bit order between hierarchyHow to fix Error(23782): Failed to find an expected reportSolvedQuartus 22.1 and 23.1 Synthesis ErrorCould not link 'vsim_auto_compile.dll' error troubleshooting.Failed to run ip-setup-simulation: