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Altera_Forum
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12 years ago

ROM at ModelSim - data port is in High-Z State

Hi all. Im new to FPGAs. I have built some circuit with ROM memory (added with MegaWizard). The problem is memory output port is in the High-Z state all the time. I have connected clock to 50...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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Please help me, I will go crazy :| Timings are OK. Whats wrong with configuration?

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Configuration looks OK. Check Memory List in Modelsim.