Reversing bits in a bus in verilog...

Question

I was wondering about the easy way to reverse bits in a bus in Verilog. Here is the code I wrote:

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if (rev) begin

out[29:0] <= inp[0:29]; // Reverse video data buss bit order

end else begin // !rev

out[29:0] <= inp[29:0]; // Normal video data buss bit order

end

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The second line came up with a compile error: Part select direction is opposite...

Is there a quick way to do this without writing out each wire?

altera_forum · Answer

In VHDL a for loop is necessary for the bit reversal, I think, it's also the case in Verilog.

altera_forum · Answer

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In VHDL a for loop is necessary for the bit reversal, I think, it's also the case in Verilog.

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Are you saying to place :

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for ( n=0 ; n < 30 ; n=n+1 ) begin

out[n] <= inp[29-n]; // Reverse video data buss bit order

end

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in place of the -> out[29:0] <= inp[0:29];

I'm assuming my Verilog use of a 'for loop' here is correct....

altera_forum · Answer

Yes, it looks OK.

altera_forum · Answer

welll.. there's a bug in Quartus ... if you have: wire [9:0] a; wire [0:-9] b;  then: assign a=b; causes a flip.

altera_forum · Answer

If you can use SystemVerilog, its simple to use the streaming operator  out = {&lt;&lt;{inp}};  // right to left streaming

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