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Altera_Forum
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14 years ago

Reversing bits in a bus in verilog...

I was wondering about the easy way to reverse bits in a bus in Verilog. Here is the code I wrote: ------------------------------------------ if (rev) begin out[29:0] <= inp[0:29]; // ...
Altera_Forum's avatar
Altera_Forum
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13 years ago

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If you can use SystemVerilog, its simple to use the streaming operator

out = {<<{inp}}; // right to left streaming

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Since this post is under "Quartus II," it's worth noting that Quartus does not support the streaming operator. It is still listed as "unsupported" in Q12.0:

http://quartushelp.altera.com/current/mergedprojects/hdl/vlog/vlog_list_sys_vlog.htm

(See section 11)

I tried it just for kicks and got a syntax error. ModelSim recognized it, though.