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Altera_Forum
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14 years ago

Reversing bits in a bus in verilog...

I was wondering about the easy way to reverse bits in a bus in Verilog. Here is the code I wrote: ------------------------------------------ if (rev) begin out[29:0] <= inp[0:29]; // ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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In VHDL a for loop is necessary for the bit reversal, I think, it's also the case in Verilog.

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Are you saying to place :

---------------------

for ( n=0 ; n < 30 ; n=n+1 ) begin

out[n] <= inp[29-n]; // Reverse video data buss bit order

end

--------------------

in place of the -> out[29:0] <= inp[0:29];

I'm assuming my Verilog use of a 'for loop' here is correct....