Retaining unused logic with Quartus?

LCELLs are not supposed to be retained if they don't do anything useful. With your HDL file open, go to Edit -> Insert -> Template and then look at the Altera attributes. There should be a number of attributes that can help. Note that your going to have problems from both ends, i.e. logic gets removed when it doesn't drive anything, as well as when it isn't driven.

Another option would be to have inputs/outputs drive them, and then assign those inputs/outputs to be virtual pins(so they don't have to use real I/O). That may be the best solution for what your trying to do.

And why are you trying to add logic that does nothing?

The Quartus setting on the help page copied below should take care of the outputs that don't drive anything.

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Preserve Fan-out Free Register Node logic option

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This option can be set in the Assignment Editor.

A logic option that specifies that the register should be preserved in the design even when it becomes fan-out free.

This option is available for supported device (Arria GX, Cyclone II, Cyclone III, HardCopy, MAX II, Stratix II, Stratix III, and Stratix IV) families.

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Another option would be to have inputs/outputs drive them, and then assign those inputs/outputs to be virtual pins(so they don't have to use real I/O). That may be the best solution for what your trying to do.

And why are you trying to add logic that does nothing?

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Who says that my logic does nothing? I merely said that it wasn't connected to anything. ;)

As for your virtual pin suggestion, I'm pleasantly surprised that it seems to have worked. Not exactly what I had in mind, but quite suitable, I think. Thanks for your help.

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The Quartus setting on the help page copied below should take care of the outputs that don't drive anything.

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I tried what you suggested, but without success, probably because the logic had both zero fan-in and zero fan-out. I appreciate the suggestion though.

You can also try the synthesis keep and synthesis preserve directives in your HDL code. This should instruct the compiler not to remove them.

Brad's suggestion in general should work. You would also need to assignments for the other compiler options that remove unused logic.

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You can also try the synthesis keep and synthesis preserve directives in your HDL code. This should instruct the compiler not to remove them.

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I can push the logic through Synplify synthesis with no problem, as can be verified from the .vqm. As for constraints to protect it from there on, once it's inside Quartus, nothing that I tried seemed to work.

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Brad's suggestion in general should work. You would also need to assignments for the other compiler options that remove unused logic.

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I set up the following through the Assignment Editor, but it didn't prevent the removal:

set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE ON -to "test_block:stub"

If that's not what I should have been writing, or if you can recommend something else, I'm all ears.

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I set up the following through the Assignment Editor, but it didn't prevent the removal:

set_instance_assignment -name PRESERVE_FANOUT_FREE_NODE ON -to "test_block:stub"

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I don't know if it's a bug in Quartus, but I've also seen cases where no assigment or attribute would prevent a fanout-free register to be removed.

But note that you should use the "noprune" attribute. Otherwise, according to the manul, it could be removed early before synthesis. But that didn't help to me in some cases.

It was using the Web free version that doesn't support virtual pins. So the only solution for me was to either tap it with Signal-Tap (but then, it is not fanout free anymore), or using WYSIWYG primitives in a VQM file.

If you try the latter, note that Quartus makes a big difference between VQM and plain Verilog files. What makes the difference is not the file extension, you need to tell Quartus is a VQM file. You might also need to disable fitter WYSIWYG optimizations.

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May I ask what logic that is entirely unattached to anything else in a design is good for?

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You may safely assume that I'm up to no good. ;)

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Some days ago I tried to fill up an FPGA up to 100% LE usage by implementing weird logic connected to nothing. The only way to have the logic really be implemented was to connect it to pins.

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I've found different results depending on the vendor tools (i.e. Xilinx), but in this case virtual pins also do the trick, as pointed out by Rysc above.