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Altera_Forum
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17 years ago

Retaining unused logic with Quartus?

I have some logic that is entirely unattached to anything else in a design (and intentionally so), but I don't want Quartus to remove it. It looks fine in the synthesized .vqm, but it gets yanked be...
Altera_Forum's avatar
Altera_Forum
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17 years ago

You can also try the synthesis keep and synthesis preserve directives in your HDL code. This should instruct the compiler not to remove them.

Brad's suggestion in general should work. You would also need to assignments for the other compiler options that remove unused logic.