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Altera_Forum
Honored Contributor
Honored ContributorReplacing a process with 1-port RAM
i have process I need to now implement as ROM.
process (count, outi, run) --converter
begin
if (run = '1') then -- run is a physical switch
case count is -- count is the current value of a 2 bit counter
when "00" =>
outi <= "1000";
when "01" =>
outi <= "0100";
when "10" =>
outi <= "0001";
when "11" =>
outi <= "0010";
when others =>
outi <= "0000";
end case;
end if;
end process;
21 Replies
Altera_Forum--- Quote Start --- Count doesnt have an initial value, or a reset value, hence it will initialise (in simulation) to 'U' You also have other issues: 1. You should create logic divided clocks- they are prone to timing issues on hardware 2/ do not use "and" with the clock 3. its better to separate asynchronous and synchronous logic into different processes. --- Quote End --- I changed count to now be
1. I'm sure what logic divided clock means. 2. I changed it and used if conditions instead. 3. I've done that also The output is still U for all of the U1 signals after running sim and count still initialises as Usignal count : std_logic_vector (1 downto 0) :="00";- Altera_Forum
Your "current_clk" is a logic generated clock, because you used logic to generate a clock
Much better to use clock enables instead. - Altera_Forum
I made two process for different frequencies now the output looks time shifted but I don't really care about that for no. I still can't see any of U1's signals, they're all still U or UU or UUUU. is it that its just not possible or something?
- Altera_Forum
Did you set and initial value for count? or reset it?
- Altera_Forum
yeah
signal count : std_logic_vector (1 downto 0) :="00"; - Altera_Forum
And where is the testbench code? have you tried testing in modelsim?
- Altera_Forum--- Quote Start --- And where is the testbench code? have you tried testing in modelsim? --- Quote End --- I just made this
step and led show up as "UU" and "UUUU" but the signal assignments work. But if i use the university program simulation, the main program works fine (apart from the Us I get for the ROM)library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity test is end test; architecture Behavioral of test is component tet is Port ( CLOCK_50 : in std_logic; run : in std_logic; dir : in std_logic; step : out std_logic_vector (1 downto 0); led : out std_logic_vector(3 downto 0):="1000"; slow_fast : in std_logic ); end component; signal run_a : std_logic := '1'; signal clk_a : std_logic := '0'; signal dir_a : std_logic := '1'; signal slow_a : std_logic := '0'; constant clkp : time := 20ps; signal step_a : std_logic_vector (1 downto 0); signal led_a : std_logic_vector (3 downto 0); begin A1 : tet port map (clk_a, run_a, dir_a, step_a, led_a, slow_a ); clk_proc : process begin clk_a <= '0'; wait for clkp/2; clk_a <= '1'; wait for clkp/2; end process; stim_proc: process begin wait for 20 ps; run_a <='1'; dir_a <= '1'; slow_a <= '0'; wait for 300 ps; run_a <='0'; wait for 300 ps; run_a <= '1'; dir_a <= '0'; wait for 300 ps; slow_a <= '1'; wait for 300 ps; end process; end Behavioral; - Altera_Forum
Did you assign any values to the rom? without specifying the contents, it will simulate with all U
- Altera_Forum--- Quote Start --- Did you assign any values to the rom? without specifying the contents, it will simulate with all U --- Quote End --- yeah i did. It was in my first post
- Altera_Forum
You first post shows code that would infer a rom from code. The later code shows a component called "rom" with no port called "count"
Please post ALL of your code. Why not post the project?
