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And where is the testbench code? have you tried testing in modelsim?
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I just made this
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
end test;
architecture Behavioral of test is
component tet is
Port ( CLOCK_50 : in std_logic;
run : in std_logic;
dir : in std_logic;
step : out std_logic_vector (1 downto 0);
led : out std_logic_vector(3 downto 0):="1000";
slow_fast : in std_logic
);
end component;
signal run_a : std_logic := '1';
signal clk_a : std_logic := '0';
signal dir_a : std_logic := '1';
signal slow_a : std_logic := '0';
constant clkp : time := 20ps;
signal step_a : std_logic_vector (1 downto 0);
signal led_a : std_logic_vector (3 downto 0);
begin
A1 : tet port map (clk_a, run_a, dir_a, step_a, led_a, slow_a );
clk_proc : process
begin
clk_a <= '0';
wait for clkp/2;
clk_a <= '1';
wait for clkp/2;
end process;
stim_proc: process
begin
wait for 20 ps;
run_a <='1';
dir_a <= '1';
slow_a <= '0';
wait for 300 ps;
run_a <='0';
wait for 300 ps;
run_a <= '1';
dir_a <= '0';
wait for 300 ps;
slow_a <= '1';
wait for 300 ps;
end process;
end Behavioral;
step and led show up as "UU" and "UUUU" but the signal assignments work.
But if i use the university program simulation, the main program works fine (apart from the Us I get for the ROM)
Honored Contributor
