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Count doesnt have an initial value, or a reset value, hence it will initialise (in simulation) to 'U'
You also have other issues:
1. You should create logic divided clocks- they are prone to timing issues on hardware
2/ do not use "and" with the clock
3. its better to separate asynchronous and synchronous logic into different processes.
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I changed count to now be
signal count : std_logic_vector (1 downto 0) :="00";
1. I'm sure what logic divided clock means.
2. I changed it and used if conditions instead.
3. I've done that also
The output is still U for all of the U1 signals after running sim and count still initialises as U
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