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Scarlet's avatar
Scarlet
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2 years ago

Strange issues on FPGA

Hi All, I wrote a simple finite state machine Verilog code and ran it on the FPGA, but it never runs stably. My environment: - MAX10 10m08 EVB - Quartus Prime Lite 23.1.1 My Verilog Code: ...
Compilation
Hdl
FvM's avatar
FvM
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2 years ago

Hi,
we see that unexpected state enters on DIO_Tick edge. Where is this signal originated? Guess it's also asynchronous and needs synchronization.

Scarlet's avatar
Scarlet
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2 years ago
@FvM wrote:

Hi,
we see that unexpected state enters on DIO_Tick edge. Where is this signal originated? Guess it's also asynchronous and needs synchronization.

DIO_Tick comes from the DIO card of the PC.

I found that both of these issues may stem from errors in receiving external signals. I suspect that the data_valid is causing the FSM to jump to an illegal state, leading to the incorrect Tick_FPGA signal.

In designing the FPGA to receive external signals, I'm not experienced enough, which has led to unexpected errors even in simple state machines.

Currently, I have resolved the timing issues related to external signal processing.