New Contributor
Super ContributorHi,
Usually we only able to follow the coding style mention here https://www.intel.com/content/www/us/en/docs/programmable/683082/22-1/inserting-hdl-code-from-a-provided-template.html if you want to infer the ram. If you try to use different way, it will not be able to infer the ram.
Have you also try try the IP instead of writing the code?
Thanks
New ContributorThank you for your reply.
My issue is not that the tool does not properly infer the RAMs. I am using Intel's IP named "On-Chip Memory (RAM or ROM) IP" which is found in the Platform Designer.
The issue is that, if I use pipeline stages and interconnects to connect different agents to different SRAMs, the M20K block packing to implement these SRAMs has an efficiency of 80%, i.e. 20% of the available M20K capacity is wasted, if I am using 32-bit wide ports.
I noticed that the efficiency was nearly 100% when I had no pipeline stages and if only one agent connected to each SRAM.
Efficiency dropped to 80% if multiple agents connect to each SRAM (i.e. an interconnect is needed) and/or I add pipeline stages between the agent and the SRAM ports.
