Forum Discussion

zjj's avatar
zjj
Icon for Occasional Contributor rankOccasional Contributor
25 days ago
Solved

ram retiming

In my project with agilex7, I have added the following the setting:

set_global_assignment -name ALLOW_RAM_RETIMING ON

so I think quartus tool should execute the ram retiming

But the fit.retimg.rpt still report the following retiming restriction:

; Retiming Restrictions at Register #1: ; x_blk_fb|x_tdb|x_tdb_rctrl|x_tdb_rctrl_mporead|x_tdb_rctrl_mporead_pld|x_mpo_pld_fifo|x_scfifo|auto_generated|dpfifo|FIFOram|altera_syncram_impl1|ram_block2a1025 ;

; Node is in a RAM or DSP block that cannot be retimed. ;

; Manually adjust your RTL design to add additional registers or re-position registers along the path to balance slack ;

so how to fix the ram retiming restriction?

 

Timing
  • KennyT_altera's avatar
    KennyT_altera
    22 days ago

    H Zjji, 

     

    Enabling ALLOW_RAM_RETIMING allows Quartus to retime across RAMs when the RAM implementation supports it, but it does not guarantee that every RAM/FIFO instance can be retimed. In this case, the reported node is inside the FIFO RAM hard block, so Quartus cannot move registers through that block boundary.

    To improve timing, the recommended action is to modify the RTL/IP structure by enabling optional RAM/FIFO input/output registers, or by adding pipeline registers before or after the FIFO RAM path. This is why the report suggests manual register repositioning even though RAM retiming is enabled.

     

    Thanks,

    Best regards,
    Kenny

     

2 Replies

  • KennyT_altera's avatar
    KennyT_altera
    Icon for Super Contributor rankSuper Contributor
    22 days ago

    H Zjji, 

     

    Enabling ALLOW_RAM_RETIMING allows Quartus to retime across RAMs when the RAM implementation supports it, but it does not guarantee that every RAM/FIFO instance can be retimed. In this case, the reported node is inside the FIFO RAM hard block, so Quartus cannot move registers through that block boundary.

    To improve timing, the recommended action is to modify the RTL/IP structure by enabling optional RAM/FIFO input/output registers, or by adding pipeline registers before or after the FIFO RAM path. This is why the report suggests manual register repositioning even though RAM retiming is enabled.

     

    Thanks,

    Best regards,
    Kenny