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Altera_Forum's avatar
Altera_Forum
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15 years ago

qxp file issues

Hi,

I am having a problem in Quartus with the .qxp files that I need to generate. Currently I have a project in Quartus which is 100% complete, simulated, fully constrained and meets timing and all the rest. I need to pass this design to another group as they need to add their modules to it. The problem is that they are not allowed to see my VHDL source code, which is making life a little difficult.

I have been reading the quartus ii incremental compilation for (http://www.altera.com/literature/hb/qts/qts_qii51015.pdf)

hierarchical and team-based design (http://www.altera.com/literature/hb/qts/qts_qii51015.pdf) handbook to get some help. What I am doing is generating a qxp file for each component in the design. I have a project layed out as follows:

Top Level

Interface to control interface 1

Interface to control interface 2

Interface to control interface 3

Interface to control interface 4

What I have done is set each of the lower level components as the top level, compl¡led the design and exported it as a design partition. I repeat this for all 4 lower level components. Then I remove the original VHDL files from the project and add the 4 qxp files. When I compile the design again with the original top level as the top level (and instaiating the components as before), it seems that the component 1 works as expected on the board, but the remaining components do not. Upon closer inspection, I noticed that during the compilation process it was ignoring some of the 'create clock' statements in my .sdc file and these clocks as it happened are used in the components which do not work. I cannot understand why it gives me this problem for only certain components.

Anyway, could someone please advise me as to whether this approach is the best way to achieve what i am trying to do. If it is not the most efficient way or I am not doing it correctly please advise.

I was playing around with partitions, and after creating a partition for the respective components, and enabling incremental compilation, it starts giving me fatal errors, which i haven´t fully understood yet. I am obviously doing something badly worng. I´d be very grateful for any help.

Many thanks

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  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi again,

    I updated to Quartus 9.1 SP2 and everything is now working correctly. I was suprised at this. Beforehand I was using v9.1 without any sevice pack.

    For now everything seems to be in order. I´ll post back if anything else unexpected happens.

    many thanks for all the help
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    I also got a speedy reply from Altera mysupport on this, shown below.

    I had things working with my old approach after installing service pack 2 but have now used their recomended approach which was slightly different and it is also working, so I will adopt this approach.

    Here is the response from teh Altera expert, in case anyone else has a similar issue in teh future:

    --- Quote Start ---

    I have referred to your post on the Altera Forum and my only comment is the toplevel is supposed to act as a wrapper for the lower level modules, you therefore need to compile each lower level module in the full design, and export each in turn from the full compilation but with the modules left blank or black boxes.

    For example create 4 separate projects.

    Project 1

    Top Level (wrapper)

    Interface to control interface 1 (source code)

    Interface to control interface 2 (leave empty)

    Interface to control interface 3 (leave empty)

    Interface to control interface 4 (leave empty)

    Then export the partition for interface 1.

    Like wise.

    Project 2

    Top Level (wrapper)

    Interface to control interface 1 (leave empty)

    Interface to control interface 2 (source code)

    Interface to control interface 3 (leave empty)

    Interface to control interface 4 (leave empty)

    Then export the partition for interface 2.

    Continue this for all 4 modules.

    Your final project will now be as followings.

    Top Level (wrapper)

    Interface to control interface 1 (imported QXP)

    Interface to control interface 2 (imported QXP)

    Interface to control interface 3 (imported QXP)

    Interface to control interface 4 (imported QXP)

    This is covered in the Incremental compilation QII handbook.

    http://www.altera.com/literature/hb/qts/qts_qii51015.pdf

    --- Quote End ---

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hi again,

    Just one final question with regard to this issue.

    I have sucessfully compiled my partitioned design but in certain partitions, I have some ports which are unused at the moment. They seem to appear as dangling ports in the pin planner even though they are not actual I/O´s.

    Could someone explain to me what a dangling port is? an unused one?

    Also they are interfering with timequest and it is complaining of 100´s of unconstrained paths, even though the design was fully constrained before partitioning. UJpon inspection they are mostly due to dangling ports.

    I would be grateful if someone could let me know the best way to deal with dangling ports and explain exactly how they come to be?

    Many thanks for the help.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Hi again,

    Just one final question with regard to this issue.

    I have sucessfully compiled my partitioned design but in certain partitions, I have some ports which are unused at the moment. They seem to appear as dangling ports in the pin planner even though they are not actual I/O´s.

    Could someone explain to me what a dangling port is? an unused one?

    Also they are interfering with timequest and it is complaining of 100´s of unconstrained paths, even though the design was fully constrained before partitioning. UJpon inspection they are mostly due to dangling ports.

    I would be grateful if someone could let me know the best way to deal with dangling ports and explain exactly how they come to be?

    Many thanks for the help.

    --- Quote End ---

    Hi,

    when you define a design partition Quartus preserves the interface of the partition. Unused ports are no longer removed. If you e.g. have outputs which are not used , they will be left as dangling ports in your desgin. If it is ok that they are not used you can ignore the dangling ports. Keep also in mind that no cross-partition optimization takes place, that could lead to unused inputs or inputs which are stucked to "1" or "0".

    Kind regards

    GPK
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for the reply pletz.

    Is there anyway to prevent the dangling ports from appearing in the pin planner. It´s just that i have to pass my part of the design onto another group and it just looks a bit untidy that they appear there when there are not really inputs and outputs. I tried simply deleting them but they reappear after the next compilation.

    I understand that they are nothing to worry about but would be interested to know if there is a simple way to prevent them from appearing in the pin planner.

    Manya thanks again,
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Thanks for the reply pletz.

    Is there anyway to prevent the dangling ports from appearing in the pin planner. It´s just that i have to pass my part of the design onto another group and it just looks a bit untidy that they appear there when there are not really inputs and outputs. I tried simply deleting them but they reappear after the next compilation.

    I understand that they are nothing to worry about but would be interested to know if there is a simple way to prevent them from appearing in the pin planner.

    Manya thanks again,

    --- Quote End ---

    Hi,

    it surpised me that you could see the internal dangling port in the pin planner. My understanding was that you could see only ports of your design in the pin planner. I never saw internal

    signals in the planning tool ????

    Kind regards

    GPK