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Hi again,
Just one final question with regard to this issue.
I have sucessfully compiled my partitioned design but in certain partitions, I have some ports which are unused at the moment. They seem to appear as dangling ports in the pin planner even though they are not actual I/O´s.
Could someone explain to me what a dangling port is? an unused one?
Also they are interfering with timequest and it is complaining of 100´s of unconstrained paths, even though the design was fully constrained before partitioning. UJpon inspection they are mostly due to dangling ports.
I would be grateful if someone could let me know the best way to deal with dangling ports and explain exactly how they come to be?
Many thanks for the help.
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Hi,
when you define a design partition Quartus preserves the interface of the partition. Unused ports are no longer removed. If you e.g. have outputs which are not used , they will be left as dangling ports in your desgin. If it is ok that they are not used you can ignore the dangling ports. Keep also in mind that no cross-partition optimization takes place, that could lead to unused inputs or inputs which are stucked to "1" or "0".
Kind regards
GPK
Honored Contributor
