QUIP: add_new_cell supports only subset of architecture?

What is it you're trying to do? I'm guessing very few people who watch this board do much Chip Planner Tcl scripting. I've done it a few times, and it's only been a minor tweak on scripts I've created from the Change Manager. But that's really what the ECO's of the Chip Planner are designed for. It seems almost like you're trying to create a design with the Chip Planner, and a large one at that(i.e. I'm sure people have created small designs that are a handful of LEs, like a special clock mux or something...)

If you describe your goals, there might be a better way to do it.

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I'm guessing very few people who watch this board do much Chip Planner Tcl scripting.

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I understand. Is there a better forum for this?

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I've done it a few times, and it's only been a minor tweak on scripts I've created from the Change Manager. But that's really what the ECO's of the Chip Planner are designed for.

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I suppose I was under the impression that TCL didn't merely provide a public API for Quartus, but actually tied in to its core functionality. So although I knew that Chip Planner looked at changes as ECOs, I assumed that the TCL interface would open things up and give the kind of flexibility and control that I'm used to with XDL in the Xilinx world.

The academic side of me would like to see that kind of control for the benefit of all the router and placer papers out there, almost invariably built on simplistic assumptions about the architectures, and ultimately unusable in the real world. In general when I've wanted a router or placer that could work with real architectures, I've had to write my own, and that's a shame because my expertise is more with the underlying data than with the placing and routing algorithms. If there had been usable tools out there, I would have loved to simply use them.

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It seems almost like you're trying to create a design with the Chip Planner, and a large one at that.

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Now that you mention it, I can see where you might get that impression. I'm not actually trying to create large designs from scratch, but I am interested in full control of every configurable part of the device. I want to be able to exercise ever instance of every cell type, ultimately including all of the detailed routing (though I know that TCL does not allow that).

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If you describe your goals, there might be a better way to do it.

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Yeah, I suppose I should explain where I'm coming from. I'm working on a DARPA project that needs to determine that configured FPGAs have not been accidentally or maliciously compromised and can be trusted. To that end, if something could conceivably be used in a compromising fashion, then I want to understand and exercise it.

The architecture definitions, and the kinds of output than I can get from TCL are great, but although they give me a lot of information and reporting capability, they give me much less in the way of control. I'll take just as much rope as I can get, with no fear of accidentally hanging myself.

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Is there a better forum for this?

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Very unlikely

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I'm working on a DARPA project that needs to determine that configured FPGAs have not been accidentally or maliciously compromised and can be trusted. To that end, if something could conceivably be used in a compromising fashion, then I want to understand and exercise it.

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That's an understandable motivation. In this case, it may be insufficient to deal with the supported vendor tools. I fear, you have to understand the binary configuration bitsrtreams and the underlying hardware details, both completely undocumented.

If this has $ or strategic value, I would try to work with Altera directly on your goals. I know that may sound harsh, but you're probably asking for a lot of information, work, etc. and Altera is a business at the end of the day. (I kind of get what you're doing, but the term "maliciously compromised" can mean a lot of different things, and probably does.) If anything, Altera may like helping projects that may one day help Altera(especially when coming from somewhere so well respected...).

One thing I was going to say when I thought you were just trying to build a design, was to work with the tools, rather than try to understand everything they do. For example, rather than entering LUTs into the Chip Planner, learn to build them in source and then place them with assignments. The nice thing about this is the tools work much better with you. Even something like the ALM is much more complex than the old days of just a 4-input LUT and a carry-chain. I'm still finding out rules or how things are done that aren't quite what I expected. Now, if you're trying to be exhaustive in coverage and understand every scheme, that's not going to work, but it may help a little. (For example, if you're building test logic, don't build it completely as an ECO, build it as controlled source.) Just a thought. Good luck.

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If this has $ or strategic value, I would try to work with Altera directly on your goals. I know that may sound harsh, but you're probably asking for a lot of information, work, etc. and Altera is a business at the end of the day.

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There is no monetary value at present. As you say there would certainly be a lot of work involved, though the intent was for me to do it, rather than push it off on someone else. That's partly why my preferred approach would have been to make use of existing tools.

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(I kind of get what you're doing, but the term "maliciously compromised" can mean a lot of different things, and probably does.)

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It can indeed mean many things. In general we're just interested in added, removed, or modified functionality. But as you're surmising, that can result in something failing to work at a critical time, or generating erroneous results, or leaking keys, or sucking power too quickly.

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One thing I was going to say when I thought you were just trying to build a design, was to work with the tools, rather than try to understand everything they do. For example, rather than entering LUTs into the Chip Planner, learn to build them in source and then place them with assignments.

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That is indeed part of what I'm doing. But for everything that cannot be added or described at the WYSIWYG level, I'll have to look elsewhere. I was kind of hoping for one-stop-shopping. ;)

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(For example, if you're building test logic, don't build it completely as an ECO, build it as controlled source.)

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I think my misunderstanding comes in part from what I'm accustomed to in the Xilinx world, and in part from my failure to take "ECO" literally. I figured Altera was simply acknowledging that users would generally only use Chip Editor for small-scale changes, but I didn't realize that Chip Editor was effectively limited to those kinds of changes. I now know better.

I appreciate the comments and suggestions.

The ::quartus::chip_editor package also supports adding I/Os but will not allow you to add any arbitrary BLOCK_INSTANCE into the design. On Stratix® II FPGA devices only LCELL_FF, LCELL_COMBS and I/Os are supported for addition and deletion. ECOs can modify properties on several other blocks but due to the complicated rules governing other block types adding or removing them is not supported.

For I/Os specifically you need to use the “add_new_io” command rather than “add_new_cell”. For example:

add_new_io -cell_name new_cell -location IOC_X0_Y2_N0 -direction bidir