Forum Discussion
Altera_Forum
Honored Contributor
17 years ago --- Quote Start --- I'm guessing very few people who watch this board do much Chip Planner Tcl scripting. --- Quote End --- I understand. Is there a better forum for this? --- Quote Start --- I've done it a few times, and it's only been a minor tweak on scripts I've created from the Change Manager. But that's really what the ECO's of the Chip Planner are designed for. --- Quote End --- I suppose I was under the impression that TCL didn't merely provide a public API for Quartus, but actually tied in to its core functionality. So although I knew that Chip Planner looked at changes as ECOs, I assumed that the TCL interface would open things up and give the kind of flexibility and control that I'm used to with XDL in the Xilinx world. The academic side of me would like to see that kind of control for the benefit of all the router and placer papers out there, almost invariably built on simplistic assumptions about the architectures, and ultimately unusable in the real world. In general when I've wanted a router or placer that could work with real architectures, I've had to write my own, and that's a shame because my expertise is more with the underlying data than with the placing and routing algorithms. If there had been usable tools out there, I would have loved to simply use them. --- Quote Start --- It seems almost like you're trying to create a design with the Chip Planner, and a large one at that. --- Quote End --- Now that you mention it, I can see where you might get that impression. I'm not actually trying to create large designs from scratch, but I am interested in full control of every configurable part of the device. I want to be able to exercise ever instance of every cell type, ultimately including all of the detailed routing (though I know that TCL does not allow that). --- Quote Start --- If you describe your goals, there might be a better way to do it. --- Quote End --- Yeah, I suppose I should explain where I'm coming from. I'm working on a DARPA project that needs to determine that configured FPGAs have not been accidentally or maliciously compromised and can be trusted. To that end, if something could conceivably be used in a compromising fashion, then I want to understand and exercise it. The architecture definitions, and the kinds of output than I can get from TCL are great, but although they give me a lot of information and reporting capability, they give me much less in the way of control. I'll take just as much rope as I can get, with no fear of accidentally hanging myself.