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If this has $ or strategic value, I would try to work with Altera directly on your goals. I know that may sound harsh, but you're probably asking for a lot of information, work, etc. and Altera is a business at the end of the day.
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There is no monetary value at present. As you say there would certainly be a lot of work involved, though the intent was for me to do it, rather than push it off on someone else. That's partly why my preferred approach would have been to make use of existing tools.
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(I kind of get what you're doing, but the term "maliciously compromised" can mean a lot of different things, and probably does.)
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It can indeed mean many things. In general we're just interested in added, removed, or modified functionality. But as you're surmising, that can result in something failing to work at a critical time, or generating erroneous results, or leaking keys, or sucking power too quickly.
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One thing I was going to say when I thought you were just trying to build a design, was to work with the tools, rather than try to understand everything they do. For example, rather than entering LUTs into the Chip Planner, learn to build them in source and then place them with assignments.
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That is indeed part of what I'm doing. But for everything that cannot be added or described at the WYSIWYG level, I'll have to look elsewhere. I was kind of hoping for one-stop-shopping. ;)
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(For example, if you're building test logic, don't build it completely as an ECO, build it as controlled source.)
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I think my misunderstanding comes in part from what I'm accustomed to in the Xilinx world, and in part from my failure to take "ECO" literally. I figured Altera was simply acknowledging that users would generally only use Chip Editor for small-scale changes, but I didn't realize that Chip Editor was effectively limited to those kinds of changes. I now know better.
I appreciate the comments and suggestions.
Honored Contributor
