Question regarding to PLL of Cyclone IV

Have you confirmed that your received data is being captured by a clock that is centered in the data eye pattern correctly?

For 160MHz data streams you would normally send the clock with the data, i.e., use source-synchronous clocking.

A master clock distributed between boards can have different phase-shifts than the data transported on cables between boards. This would result in sometimes getting ok data, while other times not.

The receiver PLL has a phase-shift option. You can program it using an ALTPLL_RECONFIG. You could sweep over the receiver data to see when you get setup/hold violations versus not. That would help you figure out the source of your problem. At that point, you can figure out what the longer-term solution is.

Cheers,

Dave

Hi Dave,

I will try to use ALTPLL_RECONFIG and let you know the results.

Many thanks.

David.

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I will try to use ALTPLL_RECONFIG and let you know the results.

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Before you do that, check whether you are actually getting data using SignalTap II. You can then look at see whether the data is being received incorrectly, or perhaps gain some insight as to your problem.

Cheers,

Dave

Hi Dave,

Yes, I can show the captured video data on LCD now.

Only problem I have is the PLL lost lock sometimes after project compilation.

Best Regards.

David.

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Yes, I can show the captured video data on LCD now.

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Ok.

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Only problem I have is the PLL lost lock sometimes after project compilation.

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But that is a different problem than your original statement: "The problem is sometimes I can capture the right data but sometimes I can’t."

If your PLL is losing lock, then of course you will lose data :)

Does your system have a local clock source? You could use that along with some counters to check for the presence of the external 40MHz clock. If it goes missing, then that would explain why your PLL unlocks. If the reference is fine, then I would look at the PLL power supply. Perhaps it is marginal.

Cheers,

Dave

Sorry for my wrong statement.

The master 40 MHZ is free running and it is always presented.

I will check the power supply of PLL.

Many thanks.

One more question:

If PLL is reset when the watch dog program detect "lock" signal is low, can PLL be reset back to preset parameters such as "phase shift"?

What is the power supply for PLL.

Many thanks.

David.

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If PLL is reset when the watch dog program detect "lock" signal is low, can PLL be reset back to preset parameters such as "phase shift"?

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It depends on the ratio of reference to output frequency.

In your case, since the reference clock is 40MHz and you create 160MHz, then the ratio is an integer, i.e., 4x. If you trigger an oscilloscope using the 40MHz clock and look at the 160MHz signal, then the phase-shift between the two should be the same between power cycles. You can however adjust that phase shift if you want to.

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What is the power supply for PLL.

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You'll have to look at the schematic. The pin connections guidelines for the part has the recommended implementation. Check that the recommendation has been followed, and probe it to see whether the voltage looks clean (not noisy).

Cheers,

Dave