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Altera_Forum's avatar
Altera_Forum
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12 years ago

Question regarding to PLL of Cyclone IV

There is a 40MHZ master clock in my system and I am using this master clock to generate a 160MHZ to capture the incoming data. The problem is sometimes I can capture the right data but sometime...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Have you confirmed that your received data is being captured by a clock that is centered in the data eye pattern correctly?

For 160MHz data streams you would normally send the clock with the data, i.e., use source-synchronous clocking.

A master clock distributed between boards can have different phase-shifts than the data transported on cables between boards. This would result in sometimes getting ok data, while other times not.

The receiver PLL has a phase-shift option. You can program it using an ALTPLL_RECONFIG. You could sweep over the receiver data to see when you get setup/hold violations versus not. That would help you figure out the source of your problem. At that point, you can figure out what the longer-term solution is.

Cheers,

Dave