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If PLL is reset when the watch dog program detect "lock" signal is low, can PLL be reset back to preset parameters such as "phase shift"?
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It depends on the ratio of reference to output frequency.
In your case, since the reference clock is 40MHz and you create 160MHz, then the ratio is an integer, i.e., 4x. If you trigger an oscilloscope using the 40MHz clock and look at the 160MHz signal, then the phase-shift between the two should be the same between power cycles. You can however adjust that phase shift if you want to.
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What is the power supply for PLL.
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You'll have to look at the schematic. The pin connections guidelines for the part has the recommended implementation. Check that the recommendation has been followed, and probe it to see whether the voltage looks clean (not noisy).
Cheers,
Dave
Honored Contributor
