Hi, I have attached the document that seeks the information related to I2C slave component and SDM IP component integration. Can you help us to resolve the requested queries ? Regards.

Hi sneha_waghI am Jingyang and I am assigned to your case.Are you trying to convert the avalon agent to an axi slave?You could try connecting an axi bridge to convert them. Avalon Agent >>> AXI Bridge Master --- AXI Bridge Slave >>> AXI Master PortThe Quartus Platform Designer would connect the Avalon to AXI .https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-platform-designer.pdfRegardsJingyang, Teh

Hi sneha_waghAny update on this case?RegardsJingyang, Teh

Hi Jingyang, Purpose of I2C Slave in our project is as below: BMC Controller on Board will read the temperature, health status of FPGA via the I2C bus. BMC Controller requests the status via I2C Bus connected to I2C slave. I2C Slave then sends this request to Processor. Processor in turn gathers the relevant information and provides the status back to I2C Slave which in turn passes this information to BMC controller via I2C bus. The I2C Slave with memory mapped master agent will not solve the purpose. There is I2C Slave IP comes along with the processor which acts as a processor subsystem IP and it is present in SDM component. If we use the in-built SDM infrastructure of Intel FPGA, we will get our purpose solved. But in our project, we are using our own Processor and not the SDM structure. Thus we need I2C Slave IP component which is exactly same as the one gets enabled when we use in-built SDM architecture. Thus I think, below infrastructure that you had suggested won't help here: Avalon Agent >>> AXI Bridge Master --- AXI Bridge Slave >>> AXI Master Port Also can you comment on mailbox-client IP integrated as a bridge between processor and SDM [SDM: Secure Device Manager is used to access Flash] ? In case of more understanding, we can have a call. Regards Sneha

Hi Sneha Yeah we could have a call. My timezone is GMT+8, how about yours? Any timeslot that is suitable for you? Could the IP you are looking for his the "i2cslave to Avalon-MM Master Bridge"? It is able to be connected to the "Mailbox Client Intel FPGA IP" and able to export as an i2c slave. The Mailbox Client Intel FPGA IP is a bridge between a host and the secure device manager (SDM). In the block diagram below the mailbox is connected to host controller but in your case you could connect it to your processor through the "i2cslave to Avalon-MM Master Bridge" https://www.intel.com/content/www/us/en/docs/programmable/683290/21-3-20-1-0/mailbox-client-fpga-ip-user-guide.html Regards Jingyang, Teh

Hi sneha_waghIs 11am GMT+8 this coming Tuesday a suitable timeslot for you to have a call?RegardsJingyang, Teh

Query related to I2C slave IP and SDM IP | Altera Community

28 Replies

tehjingy_Altera
Regular Contributor
3 years ago
Hi Sneha

Any update on the case?
Do you still need any more support for the SDM IP?

Regards
JIngyang, Teh
- sneha_wagh
  New Contributor
  3 years ago
  Hi Jingyang,
  
  I would like to understand, if we want to test the QSPI access via Mailbox client IP in simulation environment then what could be the procedure ?
  
  Also want you to show you the mailbox client subsystem connectivity and the configuration pins needed for the FLASH connection.
  
  Can we have a call on Monday at IST 10 am ?
  
  Regards
tehjingy_Altera
Regular Contributor
3 years ago
Hi Sneha

Could these document be the information that you wanted on the mail box?

Here is an example program of the mailbox.
https://community.intel.com/cipcp26785/attachments/cipcp26785/fpga-wiki/930/1/Agilex%20Mailbox%20Client%20Intel%20FPGA%20IP%20Core%20Design%20Example(QSPI%20flash%20Access%20and%20Remote%20System%20Update).pdf

Related to the signal description you could find them listed here in section 1.2:
https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/pdfs/literature/ug/archives/ug-20087-21-3-20-1-0.pdf

Regarding simulation you could follow the steps here to generate the simulation for the mailbox IP.
https://www.intel.com/content/www/us/en/docs/programmable/683102/21-3/simulating-cores.html

If not could we have a call tomorrow instead at 10am IST?

Regards
Jingyang, Teh
- sneha_wagh
  New Contributor
  3 years ago
  Hi Jingyang,
  
  Thanks for the information.
  
  After going through the documents, understood the details of design. Now as of now, I have one query:
  
  1. Lets assume that we are trying to make access to QSPI Flash with the help of Mailbox Client IP. Here, how we can test the transactions sent to mailbox client are getting converted to QSPI commands ?
  
  I.e. If we make some Avalon transactions to avmm port of the mailbox client related to QSPI access , they will eventually will transferred to QSPI pins. How to access the QSPI pins in simulation ? As the pins are not available inside DUT to view to user.
  
  To understand this, I would recommend a call.
  
  Regards
  
  Sneha
tehjingy_Altera
Regular Contributor
3 years ago
Hi Sneha

You could try out using SignalTap to probe the QSPI signals.
https://www.intel.com/content/www/us/en/docs/programmable/683819/21-3/logic-analyzer-introduction.html

Regards
Jingyang, Teh
- sneha_wagh
  New Contributor
  3 years ago
  Ok,
  
  After going through the document, can you confirm below flow ?
  
  VCS simulator pattern generator for mailbox on avalon interface -> mailbox client IP receiving the avalon signals -> SDM IP -> SDI QSPI IO pins tapped in Signal Tap Debugger -> VCS simulator analyzing the Signal Tap captured data.
  
  Also can we use this QSPI interface i.e. AVS pins of the Flash after configuration ? Or is this interface is only meant to access the flash for configuration purpose ?
  
  Regards
  
  Sneha
tehjingy_Altera
Regular Contributor
3 years ago
Hi Sneha

Yeah the flow is correct.
For the SDM QSPI flash access is mainly for configuration purpose only.

Regards
Jingyang, Teh
- sneha_wagh
  New Contributor
  3 years ago
  Thanks Jingyang,
  
  We would like to use the QSPI flash via SDM port for the general flash access also after the configuration process by our inhouse custom processor that will be part of FPGA design. Hope this is not the problem, as different Intel documents support this use case.
  
  Regards
  
  Sneha
tehjingy_Altera
Regular Contributor
3 years ago
Hi Sneha

I do not see a problem why it could not be done.
Could you share me the document that you are referring that mention this could not be done?

Regards
Jingyang, Teh
tehjingy_Altera
Regular Contributor
3 years ago
Hi

Any update on this case?

Regards
Jingyang, Teh
- sneha_wagh
  New Contributor
  3 years ago
  Hi Jingyang,
  
  Don't know why my last update did not get posted here. I was trying to say that most of the documents mentioned that with the help of mailbox client IP, any FPGA logic can access the Flash once configuration is done. The are of the flash can be divided to store configuration bitstream and the application f/w.
  
  So as of now it resolved all queries. For queries related to integration of debug trace logic, I will open a separate case. We can close this case.
  
  Regards
  
  Sneha
tehjingy_Altera
Regular Contributor
3 years ago
Hi

Since this thread been resolve, I shall set this thread to close pending. If you still need further assistance, you are welcome reopen this thread within 20days or open a new thread, some one will be right with you. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

If you happened to close this thread you might receive a survey. If you think you would rank your support experience less than 10 out of 10, please allow me to correct it before closing or if the problem can’t be corrected, please let me know the cause so that I may improve your future service experience.

Regards
Jingyang, Teh

Forum Discussion

Query related to I2C slave IP and SDM IP

28 Replies

Recent Discussions

Quartus Prim Pro: "Fatal Error: Segment Violation, Access Violation"

Using Quartus with softHSM

Crash at elaboration

Request: Questa Intel FPGA Starter Edition License for Quartus Prime 25.1 (Windows 11)

Timing analysis - long combinational path