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Vandana_GS's avatar
Vandana_GS
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1 year ago

Query regarding NCO IP supportable by Agilex 7

To generate Linear Frequency Modulated signals we have used DDS compiler with Xilinx Vivado software. We found NCO Complier for quartus prime software as we are using Agilex SOM Module FPGA: Agilex AGFB014R24B2E2V for hardware implementation. These are the questions related to it:

1) Is NCO IP supportable by Agilex 7 because in the user guide, this family is not mentioned.

2) After creation of NCO IP, the compilation was successful in Quartus prime pro and in Questa sim. But the error we are getting while start simulation.
3) Whether I have to upload any other IP generated file along with Verilog design files in Questa sim?

4) I have attached the error screenshot of Questa sim.

Please help in resolving the issue.

Thank you

Vandana G S

5 Replies

  • Hi Vandhana,

    NCO IP isn't supported in Agilex devices. That is the reason why you're observing the error.

    Kindly refer to below UG for its Device Support list.

    NCO IP UG

    Regards,

    Pavee

  • Vandana_GS's avatar
    Vandana_GS
    Icon for New Contributor rankNew Contributor

    Hi Pavee,

    We are trying to generate sine wave and cosine waveform which IP is available to perform this operation.

    Thank you

    Vandana

  • Hi Vandhana,


    Apologies for the delay.

    The NCO IP isn't supported in for Agilex devices. May I know what device you choose while generating design for NCO IP?

    And kindly let us know the Quartus version you're working with? The error you're seeing in Questasim has high chance due to device incompatibility.


    Regards,

    Pavee


    • FvM's avatar
      FvM
      Icon for Super Contributor rankSuper Contributor

      Hi,
      at first sight there are no obvious reasons why NCO IP shouldn't work for Agilex 7. The fact that it apparently compiles correctly in hardware Design seems to verify. Last IP Version was released before Agilex, but there are no hardware specific resources utilized. Embedded RAM and DSP blocks are quite similar to supported Stratix 10 series.

      There may be an Agilex specific problem with missing simulation support. To me the reported error looks more like missing generation of simulation models, not necessarily Agilex specific. You might check to generate simulation for Stratix 10. Or perform a hardware test with Signaltap on Agilex target system.

  • Hello Vandhana,


    We didn't hear from you since last update. If you have a new question, feel free to open a new thread to get the support from Altera experts. Otherwise, the community users will continue to help you on this thread.


    Thank you.