Query in the Post Route results.

Hi,

I had tried to extract the folder and open the design. However can't find the related files in screenshot:

Could you provide the missing files as well?

Thanks,

Regards,

Sheng

Hi,

May I know do you have any further concern or consideration?

Thanks,

Regards,

Sheng

Hi,

Yes, I have attached the hdl_prj folder which is having hdlsrc and quartus_prj.

Please let me know how to proceed.

Thanks,

Pravin

Hi,

your design fails timing analysis because Arria 10 maximum core clock frequency of 644 MHz is exceeded (timing analyser uses rounded value of 645.16MHz = 1/1.55ns). This causes a "minimum pulsewidth" violation for clk and a respective restricted Fmax value.
Possible contradicting reported values in timing analysis are referred. You need to solve the minimum pulsewidth problem first.

Regards
Frank

Hi,

FvM is right. You may check this document link https://cdrdv2-public.intel.com/666844/a10_datasheet-683771-666844.pdf (page 36):

As for setup slack, you may go to Assignments -> Settings -> Compiler Settings -> choose Performance

Thanks,

Regards,

Sheng

Hi,
this .sdc passes timing analysis
create_clock -name clk -period 1.56ns -waveform {0.0ns 0.78ns} [get_ports {clk}]
derive_clock_uncertainty
set_false_path -to [all_outputs]
set_false_path -from [all_inputs]

Presume NR_symbol_modulator is planned to be used inside an Arria 10 design with some kind of high speed interface. Consider that FPGA fabric side of the interface can't run above 644 MHz clock. If intended 780 MHz clock is required by interface throughput, you'll need more bits for the parallel data stream.

Hi,

May I know do you have any further update or concern?

Thanks,

Regards,

Sheng