Forum Discussion
PravinKumar
New Contributor
New ContributorQuery in the Post Route results.
May I know how implemented frequency is calculated here and why the FMax is calculated in that way. I am seeing the difference in calculating Fmax for the design. Highlighted the considered values ...
FvM
Super Contributor
Super ContributorHi,
your design fails timing analysis because Arria 10 maximum core clock frequency of 644 MHz is exceeded (timing analyser uses rounded value of 645.16MHz = 1/1.55ns). This causes a "minimum pulsewidth" violation for clk and a respective restricted Fmax value.
Possible contradicting reported values in timing analysis are referred. You need to solve the minimum pulsewidth problem first.
Regards
Frank
