Query in the Post Route results.

Hi,
this .sdc passes timing analysis
create_clock -name clk -period 1.56ns -waveform {0.0ns 0.78ns} [get_ports {clk}]
derive_clock_uncertainty
set_false_path -to [all_outputs]
set_false_path -from [all_inputs]

Presume NR_symbol_modulator is planned to be used inside an Arria 10 design with some kind of high speed interface. Consider that FPGA fabric side of the interface can't run above 644 MHz clock. If intended 780 MHz clock is required by interface throughput, you'll need more bits for the parallel data stream.