Quartus/FIR Filter/Avalon Streaming Interface/SOPC Builder

Hi dtietz

What you really need to do is build an Avalon master and/or slave interface for your device. If the data is relatively slow, you can just make the FIR a slave device, that the NIOS supplies the data one sample at a time, but usually, you want to have the FIR be a master device, which can grab data on it's one, from memory.

If you really don't need the CPU in the system, what I would recommend, is writing the re-use muxing in Verilog. This can mux the data streams, and depending on the speed of the data, keep everything running for you.

I believe, (Although I haven't used it) the fir generator, has the ability to mux 2 data paths though the same filter as well. (Again restricted by the speed of the data samples)

Pete

Thanks Pete,

Probably doing this interface in SOPC is the best way. I just don't know exactly how. If I create an Avalon master, I need to be able to interface through this externally (I believe). In other words, I need to be able to pump my data through it and into the FIR. How exactly do I do this?

From there, do I import the FIR filter into SOPC builder, or do I pull the schematic of the Avalon out to Quartus?

David

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Thanks Pete,

Probably doing this interface in SOPC is the best way. I just don't know exactly how. If I create an Avalon master, I need to be able to interface through this externally (I believe). In other words, I need to be able to pump my data through it and into the FIR. How exactly do I do this?

From there, do I import the FIR filter into SOPC builder, or do I pull the schematic of the Avalon out to Quartus?

David

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Hi David:

The more I read this, the more I realized I was probably sending you down the wrong path:

If you had a system pretty much running, and don't have a requirement for a NIOS processor and/or other items that require a Avalon bus, then SOPC is probably not required.

I've not done much schematic designs, so I can't really help you much there. However I know the Megafunction builder will build both verilog and VHDL components.

Personally, I use verilog to then interconnect the blocks the way that I require. (Writing the verilog source for the blocks that I can't find elsewhere)

SOPC builder is really for a system with a NIOS CPU, and it gives you an easy way to connect peripherals to the CPU and DATA buses. Now if you need a peripheral that isn't otherwise supplied (IE a customer FIR filter), you can write a AVALON slave component in Verilog or VHDL and using the SOPC new component wizard, to tell it what signals are AVALON slave/master signals, and what are to be exported to the top level of the design.

IE If the FIR had CPU programmable coefficients, you would create a slave bus to program the coefficients, but the data path, may actually come from and go to ADC/DAC's. These signals would then be routed to the top of the design.

I know of know way to do this in a schematic form, I've always just written the verilog at the lowest level.

Pete

Thanks again Pete,

I'm not sure if I can go the verilog way, but how do I write the avalon stuff in verilog?

David

Hi David:

The Avalon bus is described in the following doc:

www.altera.com/literature/manual/mnl_avalon_spec.pdf

I'm not aware of any verilog or vhdl examples available, but there probably are some. Can anyone from Altera point us to the good Avalon master and Avalon slave example?

If you don't mind giving me a couple of days, I'll generate an example file and post it. (If no one does it faster).

I've done both Master and Slave devices in the past, so it can be done.

With bursting master devices however, there are a few gotcha's with RAM burst boundaries that aren't described anywhere that I know of. (Except if you look through this forums about Bursting RAM issues (DDR/DDR2, etc)

Pete

I am still pretty lost.

I just don't understand why something like this is turning out to be so complicated.

Why does Quartus have an FIR filter with avalon inputs, but no device to support these inputs? It just doesn't make a lot of sense. It seems like SOPC builder is overkill, and I could just mux the channels together using VHDL, but it makes me think I'm doing something wrong when the FIR filter has those avalon inputs.