Honored Contributor
Honored ContributorHi David:
The Avalon bus is described in the following doc: www.altera.com/literature/manual/mnl_avalon_spec.pdf I'm not aware of any verilog or vhdl examples available, but there probably are some. Can anyone from Altera point us to the good Avalon master and Avalon slave example? If you don't mind giving me a couple of days, I'll generate an example file and post it. (If no one does it faster). I've done both Master and Slave devices in the past, so it can be done. With bursting master devices however, there are a few gotcha's with RAM burst boundaries that aren't described anywhere that I know of. (Except if you look through this forums about Bursting RAM issues (DDR/DDR2, etc) Pete
