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Thanks Pete,
Probably doing this interface in SOPC is the best way. I just don't know exactly how. If I create an Avalon master, I need to be able to interface through this externally (I believe). In other words, I need to be able to pump my data through it and into the FIR. How exactly do I do this?
From there, do I import the FIR filter into SOPC builder, or do I pull the schematic of the Avalon out to Quartus?
David
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Hi David:
The more I read this, the more I realized I was probably sending you down the wrong path:
If you had a system pretty much running, and don't have a requirement for a NIOS processor and/or other items that require a Avalon bus, then SOPC is probably not required.
I've not done much schematic designs, so I can't really help you much there. However I know the Megafunction builder will build both verilog and VHDL components.
Personally, I use verilog to then interconnect the blocks the way that I require. (Writing the verilog source for the blocks that I can't find elsewhere)
SOPC builder is really for a system with a NIOS CPU, and it gives you an easy way to connect peripherals to the CPU and DATA buses. Now if you need a peripheral that isn't otherwise supplied (IE a customer FIR filter), you can write a AVALON slave component in Verilog or VHDL and using the SOPC new component wizard, to tell it what signals are AVALON slave/master signals, and what are to be exported to the top level of the design.
IE If the FIR had CPU programmable coefficients, you would create a slave bus to program the coefficients, but the data path, may actually come from and go to ADC/DAC's. These signals would then be routed to the top of the design.
I know of know way to do this in a schematic form, I've always just written the verilog at the lowest level.
Pete
Honored Contributor
