Quartus12 Linux64bit + QSim Problem

Can't really help you as I'm not familiar with Qsim but I'd just avoid AHDL and Qsim alltogether, as AHDL is an Altera specific language and Qsim is a very limited tool.

You'd do better to learn Verilog/VHDL and how to use ModelSim (which is also bundled with Quartus).

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Can't really help you as I'm not familiar with Qsim but I'd just avoid AHDL and Qsim alltogether, as AHDL is an Altera specific language and Qsim is a very limited tool.

You'd do better to learn Verilog/VHDL and how to use ModelSim (which is also bundled with Quartus).

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I've solved this problem - that were crazy things in exporting ld. But there's new problem - when i was trying to create new simulation input file qsim shows error:

>> Created project: testowy (Revision: testowy)>> Running quartus compilation
>> quartus_sh --flow compile testowy -c testowy 
>> PID = 3516
*******************************************************************
Running Quartus II 64-Bit Shell
  Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
  Processing started: Sat Mar  2 15:33:24 2013
Command: quartus_sh --flow compile testowy -c testowy
Quartus(args): compile testowy -c testowy
Project Name = /home/leszek/quartus2/quartus/linux64/testowy
Revision Name = testowy
Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Quartus II Full Compilation was successful. 0 errors, 0 warnings
Evaluation of Tcl script /home/leszek/quartus2/quartus/common/tcl/internal/qsh_flow.tcl was successful
Quartus II 64-Bit Shell was successful. 0 errors, 0 warnings
  Peak virtual memory: 293 megabytes
  Processing ended: Sat Mar  2 15:33:28 2013
  Elapsed time: 00:00:04
  Total CPU time (on all processors): 00:00:01
ok
>> Node Finder found 1 nodes using "*" filter, "all" node type and "all" observable type.
>> Node Finder found 1 nodes using "*" filter, "all" node type and "pre_synthesis" observable type.
ERROR: Compiler database does not exist for revision name: testowy. At the minimum, run Analysis & Synthesis (quartus_map) with the specified revision name before using this Tcl command.

Maybe this issue u can recognized and know how to solve.

BTW.

Unfortunatelly I've to learn AHDL and this command from God :P. And my project have to be written in AHDL. Are there any other AHDL simulators except QSim? And other question is AHDL some kind of deprecated language? I know VHDL and I see that AHDL is more natural and clear language than VHDL

Yes, AHDL is pretty much a deprecated language.

AHDL (Altera HDL) is an Altera proprietary language that nobody else uses. AFAIK, Qsim is the only tool that can simulate AHDL directly.

Quartus and Qsim are likely to support it for the for the foreseeable future, but that support is quite limited and unlikely to improve.

Regarding synthesis, AHDL lacks many of the higher level constructs VHDL/Verilog have (and which keep improving).

Regarding simulation, AHDL lacks all of the facilities VHDL/Verilog have that let you have complex test benches.

Also, Qsim is quite slow and unlikely to be improved. It has been relegated to the status of "educational tool" and for a while, it looked like it was dead.

Other simulators don't support AHDL, so the only way to simulate AHDL on them is to have Quartus synthesize the design and simulate the VHDL/Verilog output, which is also a time consuming process.

VHDL and Verilog are the industry standard tools and have been for decades. They're far better supported and it's there the improvements are being made.

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Yes, AHDL is pretty much a deprecated language.

AHDL (Altera HDL) is an Altera proprietary language that nobody else uses. AFAIK, Qsim is the only tool that can simulate AHDL directly.

Quartus and Qsim are likely to support it for the for the foreseeable future, but that support is quite limited and unlikely to improve.

Regarding synthesis, AHDL lacks many of the higher level constructs VHDL/Verilog have (and which keep improving).

Regarding simulation, AHDL lacks all of the facilities VHDL/Verilog have that let you have complex test benches.

Also, Qsim is quite slow and unlikely to be improved. It has been relegated to the status of "educational tool" and for a while, it looked like it was dead.

Other simulators don't support AHDL, so the only way to simulate AHDL on them is to have Quartus synthesize the design and simulate the VHDL/Verilog output, which is also a time consuming process.

VHDL and Verilog are the industry standard tools and have been for decades. They're far better supported and it's there the improvements are being made.

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One question .. is there any possibilities to convert using for example Quartus to convert ahdl files to vhdl? Because I've got some files in ahdl and i need it in vhdl :D

Quartus synthesis will produce a VHDL/Verilog low level model of your design, no matter what the input is (VHDL, Verilog, AHDL, schematic)

It's the only way I know to "convert" AHDL to VHDL.

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Quartus synthesis will produce a VHDL/Verilog low level model of your design, no matter what the input is (VHDL, Verilog, AHDL, schematic)

It's the only way I know to "convert" AHDL to VHDL.

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So if I correctly understood, it's possible to connect in one project vhdl and ahdl files?

Yes, it is.

ModelSim will accept only accept VHDL and Verilog.

And, unless you pay for a ModelSim PE license, it will not let you even mix VHDL and Verilog in the same design.

Quartus however, will accept any mix of VHDL, Verilog, AHDL and schematic modules in a design.

And after synthesis, Quartus will produce either a VHDL or Verilog model of the synthesis result.

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Yes, it is.

ModelSim will accept only accept VHDL and Verilog.

And, unless you pay for a ModelSim PE license, it will not let you even mix VHDL and Verilog in the same design.

Quartus however, will accept any mix of VHDL, Verilog, AHDL and schematic modules in a design.

And after synthesis, Quartus will produce either a VHDL or Verilog model of the synthesis result.

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Good to hear that ;D. Thanks for your help!