Forum Discussion
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- Quartus synthesis will produce a VHDL/Verilog low level model of your design, no matter what the input is (VHDL, Verilog, AHDL, schematic) It's the only way I know to "convert" AHDL to VHDL. --- Quote End --- So if I correctly understood, it's possible to connect in one project vhdl and ahdl files?