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Can't really help you as I'm not familiar with Qsim but I'd just avoid AHDL and Qsim alltogether, as AHDL is an Altera specific language and Qsim is a very limited tool.
You'd do better to learn Verilog/VHDL and how to use ModelSim (which is also bundled with Quartus).
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I've solved this problem - that were crazy things in exporting ld. But there's new problem - when i was trying to create new simulation input file qsim shows error:
>> Created project: testowy (Revision: testowy)>> Running quartus compilation
>> quartus_sh --flow compile testowy -c testowy
>> PID = 3516
*******************************************************************
Running Quartus II 64-Bit Shell
Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
Processing started: Sat Mar 2 15:33:24 2013
Command: quartus_sh --flow compile testowy -c testowy
Quartus(args): compile testowy -c testowy
Project Name = /home/leszek/quartus2/quartus/linux64/testowy
Revision Name = testowy
Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Quartus II Full Compilation was successful. 0 errors, 0 warnings
Evaluation of Tcl script /home/leszek/quartus2/quartus/common/tcl/internal/qsh_flow.tcl was successful
Quartus II 64-Bit Shell was successful. 0 errors, 0 warnings
Peak virtual memory: 293 megabytes
Processing ended: Sat Mar 2 15:33:28 2013
Elapsed time: 00:00:04
Total CPU time (on all processors): 00:00:01
ok
>> Node Finder found 1 nodes using "*" filter, "all" node type and "all" observable type.
>> Node Finder found 1 nodes using "*" filter, "all" node type and "pre_synthesis" observable type.
ERROR: Compiler database does not exist for revision name: testowy. At the minimum, run Analysis & Synthesis (quartus_map) with the specified revision name before using this Tcl command.
Maybe this issue u can recognized and know how to solve.
BTW.
Unfortunatelly I've to learn AHDL and this command from God :P. And my project have to be written in AHDL. Are there any other AHDL simulators except QSim? And other question is AHDL some kind of deprecated language? I know VHDL and I see that AHDL is more natural and clear language than VHDL
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