Honored Contributor
Honored ContributorYes, AHDL is pretty much a deprecated language.
AHDL (Altera HDL) is an Altera proprietary language that nobody else uses. AFAIK, Qsim is the only tool that can simulate AHDL directly. Quartus and Qsim are likely to support it for the for the foreseeable future, but that support is quite limited and unlikely to improve. Regarding synthesis, AHDL lacks many of the higher level constructs VHDL/Verilog have (and which keep improving). Regarding simulation, AHDL lacks all of the facilities VHDL/Verilog have that let you have complex test benches. Also, Qsim is quite slow and unlikely to be improved. It has been relegated to the status of "educational tool" and for a while, it looked like it was dead. Other simulators don't support AHDL, so the only way to simulate AHDL on them is to have Quartus synthesize the design and simulate the VHDL/Verilog output, which is also a time consuming process. VHDL and Verilog are the industry standard tools and have been for decades. They're far better supported and it's there the improvements are being made.
