Quartus_syn and nested pragma not supported

Hi,

Pragma is not supported in pro version check this link https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/remove-non-standard-pragmas.html

Intel® Quartus® Prime Pro Edition synthesis does not support the vhdl(verilog)_input_version pragma or the library pragma. Synthesis in other Quartus software products supports these pragmas. Remove any use of the pragmas from RTL for Intel® Quartus® Prime Pro Edition migration.

Remove the pragma and just use it with other synthesis tools. Pro version is more strict.

Thanks,

Regards,

Sheng

For instance take this code which compiles for both quartus_map✔& quartus_syn✔:

library ieee;
use ieee.std_logic_1164.all;

--altera translate_off
--altera translate_on
library altera_mf;  -- Example Altera-specific library
use altera_mf.altera_mf_components.all;
--altera translate_off
--altera translate_on

But that one compiles only on quartus_map✔ and fails on quartus_syn with "unexpected end-of-file" error:

library ieee;
use ieee.std_logic_1164.all;

--pragma translate_off
--altera translate_on
library altera_mf;  -- Example Altera-specific library
use altera_mf.altera_mf_components.all;
--altera translate_off
--pragma translate_on

Hi,

The quartus_syn supports nesting but just not support pragma as mentioned in this document link https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/remove-non-standard-pragmas.html

Thanks,

Regards,

Sheng