New Contributor
Super ContributorHi,
Pragma is not supported in pro version check this link https://www.intel.com/content/www/us/en/docs/programmable/683475/19-4/remove-non-standard-pragmas.html
Intel® Quartus® Prime Pro Edition synthesis does not support the vhdl(verilog)_input_version pragma or the library pragma. Synthesis in other Quartus software products supports these pragmas. Remove any use of the pragmas from RTL for Intel® Quartus® Prime Pro Edition migration.
Remove the pragma and just use it with other synthesis tools. Pro version is more strict.
Thanks,
Regards,
Sheng
New ContributorHi Sheng,
Thanks you for the tip, even though it seems to contradict the documention: Intel® Quartus® Prime Pro Edition Help version 23.1 - vhdl_input_version Synthesis Directive & Intel® Quartus® Prime Pro Edition Help version 23.1 - library VHDL Synthesis Directive
Anyway in my case this is related to the "synthesis_off/on" directives. They are understood by the tool (and you can disable its support if needed), but contrary to others vendors tools and now old quartus_map, the quartus_syn doesn't support nesting it, as in my example.
Best regards,
--
Thierry
