New Contributor
Super ContributorI believe you are using Quartus Standard Edition and attempting to simulate using the Nativelink simulation flow.
Typically, when we run Tools → Run Simulation → RTL Simulation, the Quartus Standard Edition software automatically launches the Questa Altera Edition simulator and simulates the testbench file according to the specifications set in the Simulation settings.
I have not encountered any dependency ordering issues when using Nativelink.
Does the issue occur when you try to execute the .do file manually during simulation?
For example:
do PLL_RAM_run_msim_rtl_verilog.do
You may want to try running the example design (quartus-std-lite-pll-ram) provided in the user guide, following the steps and guidance described in the document.
Lite/Standard Edition:
https://www.intel.com/content/www/us/en/docs/programmable/703090/21-1/simulation-quick-start.html
Regards,
Richard Tan
New ContributorHello Richard,
Thank you for your suggestion. I followed through the sample design, and it seems to work, so I am discarding the possibility that this is a Nativelink issue.
While going through the error messages, I noticed that quite a few of them were about missing cxl-related packages, such as cxlip_top_pkg. As described in my other ticket (Re: Inquiry about device support for AGIB027R29A1E2VR3 in Quartus Prime Pro v25.1.0 - Intel Community), I am currently experiencing another difficulty with the IP Core CXL IP for Device Type 2 with Device Coherency (6AF7 0185) not getting recognized as licensed in the Assembler stage of the Compilation Flow.
If an IP is not fully recognized as licensed, could it also act as a possible source of missing package errors in Questa Nativelink simulation flow?
Many thanks,
