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MFILK's avatar
MFILK
Icon for New Contributor rankNew Contributor
7 years ago

Quartus PrimeLite SystemVerilog Support

Hi

I am trying to set up a project with Quartus Prime Lite Edition 18_0.

I am importing the whole design and testbench with SystemVerilog Files, also for the design files. But in the EDA Tool Settings/Design Entry/Synthesis Window (Tool = Custom) i can't choose the option system format SystemVerilog. only Verilog , VHDL, AHDL; VQM can be choosen.

How can i change this so i can use SystemVerilog also for design file entry ?

2 Replies

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    7 years ago

    That setting is for synthesizing your design in a tool other than Quartus. Are you doing that? If not, you don't need to set this. Quartus can synthesize .sv files directly.

    #iwork4intel

  • Vicky1's avatar
    Vicky1
    Icon for Regular Contributor rankRegular Contributor
    7 years ago

    Hi,

    Actually Quartus has limited support for system verilog, please refer the Intel FPGA Product catalog(attached)

    As suggested in above post Quartus can simply synthesize System verilog files(just create & save files with system verilog extension)

    Regards,

    Vicky