Forum Discussion
MFILK
New Contributor
New ContributorQuartus PrimeLite SystemVerilog Support
Hi I am trying to set up a project with Quartus Prime Lite Edition 18_0. I am importing the whole design and testbench with SystemVerilog Files, also for the design files. But in the EDA Tool Setti...
sstrell
Super Contributor
Super ContributorThat setting is for synthesizing your design in a tool other than Quartus. Are you doing that? If not, you don't need to set this. Quartus can synthesize .sv files directly.
#iwork4intel
