Quartus Prime Lite Quitting Unexpectedly During Fitter
I am trying to integrate UART (RS-232 Serial Port) Intel FPGA IP into my project on a DE10-Nano with a Cyclone V SoC. I have followed the CVSOV UART example from the design store and I have gotten to the point to where I am trying to call the HDL created by the platform designer into my top level code. However, when i try to compile my project I get a popup saying that Quartus Quit Unexpectedly and I do not get an actual error code at all. Furthermore, when I remove the line of code which calls the HDL for the UART generated by the platform designer the code will compile.
Has anyone else seen this kind of error when trying to integrate IP into a design, or am I likely integrating the IP incorrectly? I do not know what this error means.
Thank you in advance
I was able to get the project to compile after decreasing the total memory size in the On-chip Memory IP in platform designer. I decreased the memory from about 130000 bytes to 100000 bytes and this seemed to work.
Van