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Ryan-M's avatar
Ryan-M
Icon for New Contributor rankNew Contributor
1 year ago

Quartus II 18.1 "GPIO intel FPGA IP" not working.

Hello everyone,

I am planning to use the IP "GPIO intel FPGA IP" to realize Double Data Rate. When I use it, I make sure that the clock and input data for DDIO are correctly given. However, DDIO does not produce any output, and I don't know why. The following is the actual test situation in SignalTap. The clock used for testing is 400MHz, and the speed of the tested signal does not exceed 200MHz.

Development Environment:
1. Quartus II 18.1
2. FPGA Device: Arria 10

Hdl
Platform

3 Replies

  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    I run your design and notice that your design is not timing clean. (with or without signal tap). You will need to close the timing first before run signal tap.

    Have you try to run simulation to check the design function?


    Regards,

    Richard Tan


  • RichardT_altera's avatar
    RichardT_altera
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

    If you have any further questions or concerns, please don't hesitate to let us know.

    Thank you for reaching out to us!


    Best Regards,

    Richard Tan