Forum Discussion
Ryan-M
New Contributor
New ContributorQuartus II 18.1 "GPIO intel FPGA IP" not working.
Hello everyone, I am planning to use the IP "GPIO intel FPGA IP" to realize Double Data Rate. When I use it, I make sure that the clock and input data for DDIO are correctly given. However, DDIO doe...
RichardT_altera
Super Contributor
Super ContributorI run your design and notice that your design is not timing clean. (with or without signal tap). You will need to close the timing first before run signal tap.
Have you try to run simulation to check the design function?
Regards,
Richard Tan
