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jch4416's avatar
jch4416
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Quartus doesn't recognize clocks generated by division of the same master clock as synchronous

Hello,

I am working on a rather slow (1.8432MHz master clock) cpld design. There are 4 clocks that I generate by dividing the master clock by different integers. The divisions are done with synchronous counters, so the edges of each generated clock should be synchronous with the master but delayed by one clock to q time.

Are the resulting clock domains not considered synchronous? Quartus gives me warnings to that effect when I try to pass data between the various domains. Does the data from one domain require synchronization when being used by another even when the clocks are related as I explained?

I realize this is a newbie question, but I've been an analog and power guy for the last 15 years without doing much digital design.

Thanks,

Jim

5 Replies

  • RRomano001's avatar
    RRomano001
    Icon for Contributor rankContributor
    5 years ago

    Hello, when clock are divided small delay apply to output and transportation too.

    Information about language and CPLD series is missing, exact error too.

    Supposed you are using a ring divider or Johnson small delay is present from clock edge to FF Q output.

    If you are using a standard counter delay come from logic too.

    Please complete description to help address what happen.

    • jch4416's avatar
      jch4416
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Thanks for your reply. I am working with the MAX II family, an EPM570 cpld, and coding in Verilog.

      Here is the error message:

      Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 17 asynchronous clock domain interface structure(s) related to this rule.

      I have my clocks defined in the sdc file as shown below. All are integer divisions of the same master and the dividers are synchronous counters. I changed the divisor on the last one just for the constraint because Quartus can't seem to deal with very slow clocks

      ----------------------------------------------------------------------------

      create_clock -name {cpld_master_clock} -period 542.000 -waveform { 0.000 271.000 } [get_nets {cpld_master_clock}]


      #**************************************************************
      # Create Generated Clock
      #**************************************************************

      create_generated_clock -name {uart_rx_clock} -source [get_nets {cpld_master_clock}] -divide_by 2 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV2|clk_out}]
      create_generated_clock -name {uart_tx_clock} -source [get_nets {cpld_master_clock}] -divide_by 32 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV3|clk_out}]
      create_generated_clock -name {millisec_clock} -source [get_nets {cpld_master_clock}] -divide_by 1920 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV4|clk_out}]
      create_generated_clock -name {heartbeat_clock} -source [get_nets {cpld_master_clock}] -divide_by 3840 -master_clock {cpld_master_clock} [get_registers {clock_divider:CDIV5|clk_out}]

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    The potential cause of this warning could be either


    Cause #1: In the current design, the Design Assistant found the specified number of structures where single-bit data is transferred between asynchronous clock domains, but none of the data bits are synchronized. To reduce metastability problems, each data bit should be synchronized with two or more cascading registers in the receiving asynchronous clock domain. The submessage(s) of this message list the structure(s) that the Design Assistant found.


    >> Synchronize all the data bits.


    Cause #2: In the current design, the Design Assistant found the specified number of structures where multiple-bit data is transferred between asynchronous clock domains, but none of the data bits are synchronized. To reduce metastability problems, the data bits that act as REQ (Request) and/or ACK (Acknowledge) signals for the transfer should be synchronized with two or more cascading registers in the receiving asynchronous clock domain. The submessage(s) of this message list the structure(s) that the Design Assistant found.


    >> Synchronize the data bits that act as REQ and/or ACK signals.


    Thanks

    Best regards,

    KhaiY


  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you


    Best regards,

    KhaiY